Arduino PI Synchronous Buck Converter | DIY DC DC Converter Design

byee-diary • • 2 min read
0
I redesigned the previous Arduino Synchronous Buck Converter Design (a closed-loop step-down DC-DC switching regulator) to include synchronous rectification, analog current and voltage sensing, and dual-layer (hardware + software) fault protection capabilities and features.

Synchronous Buck Converter Circuit Schematic

The circuit diagram of Arduino Synchronous Buck Converter is shown below.

Arduino PID Synchronous Buck Converter Designed by ee-diary.net Vf L1 330uH 220 H16.000E5C ATMEL MEGA16U2 1526 PH 22X4ZA A0 A1 A2 A3 A4 A5 RESET 3.3V 5V GND GND Vin IOREF ANALOG IN POWER 47 25V VT 47 25V VT 103 103 TX RX L ~5 4 ~3 2 RX < 0 TX > 1 ~11 ~10 7 ~6 13 12 GND AREF DIGITAL(PWM~) 8 ~9 ICSP 103 ON UNO Arduino ATMEL ATMEGA328P U 0 1 2 3 4 5 6 7 8 9 10 11 12 13 A5 A4 A3 A2 A1 A0 R3 47k R4 10k LAMP 5V LOAD=5 25% VCTRL 10k VCC 1 SD 3 VB 8 HO 7 VS 6 LO 5 IN 2 COM 4 U1 IR2104S C3 100nF R1 10k Q1 IRF540N Q2 IRF540N D1 SS110 R5 10 R6 10 C4 1uF Tx Rx R7 68k R8 10k C5 100nF 1 2 5 3 4 U2 INA180A3 R9 0.01 C6 100nF R10 1k 3 2 1 8 4 U3:A LM393 96% ICTRL 10k R11 10k - + B2 5V B- B+ DC Voltage Battery Sealed Lead Acid BAT1 40V D4 SMBJ33A C8 10uF Q4 IRF4905 R13 10k D3 BZX55C12 C9 2.2nF R14 4.7 C10 100nF IN 8 SHDN 5 OUT 1 ADJ 2 V- 4 U4 LT3010 R12 84.5k R15 10k C1 470uF C2 100uF C7 470uF R16 2.7 R17 1.5k C11 100nF R18 220k R19 2.2k C12 1nF R20 10k R21 10k R2 10k D2 SS110 D5 SS110 R22 10k Q1(G) C13 2.2nF R23 4.7

1. Key Specifications & Features

  • Topology: Synchronous Buck Converter (Step-down).
  • Input Rating: 11 V to 32 V DC nominal (with Under-Voltage Lockout at 11 V and Over-Voltage Lockout at 34 V).
  • Output: 1 V to 24 V DC adjustable, rated up to 3 A continuous (driving a load such as LAMP).
  • Switching Frequency: 10 kHz (Timer1 Fast PWM from the ATmega328P).
  • Efficiency Advantage: Uses an active low-side MOSFET (Q2) instead of a conventional freewheeling diode, minimizing conduction losses (·I2 RDS(on) vs ·I VF).
  • Control Scheme: 1 kHz digital control loop using VIN feedforward plus a Proportional-Integral (PI) feedback algorithm.
  • Dual-Tier Protection:
    • Instant Hardware Trip: Dedicated analog comparator (LM393) tripping an MCU external interrupt (INT0) within microseconds to immediately shut down the gate driver.
    • Soft Software Current Foldback: Smooth voltage reduction when nearing current thresholds.
    • Input UVLO/OVLO & Output OVP/Feedback-Loss Detection

2. Functional Circuit Blocks

A. Input Power Conditioning & Protection

  • Fuse & Inrush: FUSE (5 A) protects against catastrophic short-circuits.
  • Reverse-Polarity Protection: P-channel MOSFET Q4 (IRF4905) switches on when the input polarity is correct, with Zener diode D3 (12 V) clamping VGS to a safe operating level.
  • Transient Suppression: TVS diode D4 (SMBJ33A) clamps voltage spikes and inductive ringing.
  • Bulk Filtering: Electrolytic capacitor C7 (470 µF) and ceramic C8 (10 µF) buffer pulsed switching currents.

B. Auxiliary 12 V Gate-Drive Supply

  • An LT3010 high-voltage linear regulator steps the raw input voltage down to a stable ~12 V rail (VCC).
  • This rail powers the IR2104 gate driver and the LM393 comparator, ensuring constant gate drive voltage regardless of input variations.

C. Power Stage (Synchronous Buck)

  • High-Side Switch (Q1 - IRF540N): Connects the input rail to the switching node VS during the duty cycle (D).
  • Low-Side Switch (Q2 - IRF540N): Synchronous rectifier; turns ON when Q1 turns OFF to provide a low-resistance path for the freewheeling inductor current.
  • Inductor (L1 - 330 µH): Stores magnetic energy during Q1 conduction and releases it to the load during Q2 conduction, converting the pulsed PWM voltage into smooth DC current.
  • Output Capacitor (C1 - 470 µF): Filters output voltage ripple before delivering power to the load LAMP.
  • Snubber Circuit & Damping: R14/C9 and R23/C13 absorb high-frequency ringing caused by parasitic inductances during switching transitions.

D. Gate Driver & Bootstrap Circuit

  • Driver (U1 - IR2104): Translates a single 5 V PWM signal from the Arduino (PB1/OC1A / pin 9) into complementary high- and low-side gate drives with built-in deadtime to prevent shoot-through.
  • Bootstrap Circuit (D1 & C4):
    • When Q2 is ON, VS is at 0 V, and C4 charges to ~12 V from VCC via diode D1(SS110).
    • When Q1 turns ON, VS rises to VIN. Capacitor C4 lifts the bootstrap rail VB to VIN + 12 V, enabling HO to keep Q1 fully enhanced (≈VGS 12 V).

E. Feedback & Sensing Networks

  • Output Voltage Sense: Divider R3 (47 kΩ) and R4 (10 kΩ) scales down the output voltage by a ratio of 5.7:1, fed into ADC channel PC1/ADC1 (A1) on net VF.
  • Input Voltage Sense: Divider R7 (68 kΩ) and R8 (10 kΩ) feeds the scaled input rail into PC3/ADC3 (A3).
  • High-Side Current Sense:
    • Shunt resistor R9 (10 mΩ) in series with the inductor output.
    • Current-sense amplifier U2 (INA180A3) amplifies the shunt drop by a gain of 100, providing an output of 1.0 V/A to PC2/ADC2 (A2).
  • User Controls:
    • Potentiometer VCTRL (pin A0): Sets the target output voltage (or configured via Serial).
    • Potentiometer ICTRL (pin A4): Sets the current limit threshold.

F. Hardware Fast Over-Current Protection (OCP)

  • The amplified current signal from INA180A3 current sense amplifier U2 is fed to the non-inverting input of LM393 comparator U3: A.
  • The inverting input is connected to the adjustable reference voltage set by ICTRL.
  • If load current exceeds the threshold, U3: A output immediately drives Arduino PD2/INT0 (pin 2) HIGH.
  • The Arduino executes the ISR tripISR(), immediately setting PB0 / pin 8 LOW. This pulls SD of U1 low, shutting down both IRF540N MOSFET gates in sub-microsecond time before an over-current can damage Q1 or Q2.

3. How the Closed-Loop Operation Works

The converter operates under a 50 kHz PWM power-switching frequency governed by a 1 kHz digital control loop executing on the ATmega328P microcontroller (UNO1). The control loop combines VIN feedforward, PI (Proportional-Integral) feedback, soft-start ramping, and dual-tier current protection.

Closed-Loop Operation buck converter


Step 1: Power-Up & System Initialization

  1. Pin Setup: Digital pin 8 (SD) is initially held LOW to keep the IR2104 gate driver in shutdown mode, maintaining both MOSFETs (Q1, Q2) in an OFF state.
  2. Timer Configuration: Timer1 is configured in Fast PWM Mode with ICR1 = 319, generating a precise 50 kHz PWM signal on pin 9 (IN).
  3. Input Range Check: The ADC reads VIN via divider R7/R8 on pin A3. The firmware verifies that 11 V \le VIN \le 34 V. If VIN is out of bounds, the converter remains in Under-Voltage or Over-Voltage Lockout (UVLO/OVLO).
  4. Interrupt Arming: After a 50 ms power-up delay (OCP_ARM_MS) to allow supply rails to settle, external interrupt 0 (INT0 / pin D2) is armed to enable instant hardware over-current protection.

Step 2: Target Determination & Soft-Start Ramping

  1. Target Calculation: The target voltage Vtarget is read from potentiometer VCTRL (pin A0) or received via the serial interface.
  2. Dynamic Headroom Limit: To ensure the bootstrap capacitor C4 always has sufficient time to refresh during the low-side switch conduction, Vtarget is dynamically capped:
    • $ V_{target(max)} = min(V_{in} - 1.5V, 24.0V) $
  3. Controlled Voltage Ramp: When the converter starts, Arduino pin 8 (SD) goes HIGH to enable the driver. Rather than applying a step change, the internal setpoint rampSet increases at a controlled rate of 50 V/s (RAMP_V_PER_S).
  4. Anti-Inrush Tracking: rampSet is constrained so it never leads the actual measured VOUT by more than 0.5 V (RAMP_LEAD). This prevents high inrush currents into output capacitor C1 and eliminates LC filter ringing.

Step 3: The 1 kHz Control Algorithm (sense & controlStep)

Every 1,000 µs (1 ms), the system executes a control update cycle:

  1. ADC Measurement Subroutine (sense):
    • Reads output voltage VOUT from divider R3/R4 (pin A1).
    • Reads inductor/load current IOUT from INA180A3 amplifier (pin A2, 1.0 V/A).
    • Updates filtered averages for VIN, hard-trip reference Itrip, and pot positions.
  2. VIN Feedforward (Line Regulation): The ideal duty cycle required to achieve the setpoint is calculated directly from the voltage ratio:
    • $ D_{ff} = \frac{V_{rampSet}}{V_{IN}} $
    • Benefit: If VIN fluctuates (e.g., supply voltage dips), Dff adjusts instantly in the same cycle without waiting for an output error to build up.
  3. PI Error Correction (Load Regulation):
    • Calculates loop error: e(t) = VrampSet - VOUT
    • Proportional Term: ·P(t) = KP e(t) (KP = 0.005)
    • Integral Term (with Anti-Windup): When |e(t)| , error is integrated: $I(t) = I(t-dt) + K_I /dot e(t) dt, K_I=2.0 $
  4. Duty Cycle Generation & PWM Update:
    • $ D=constraint(D_{ff}+P(t)+I(t),0.0,0.95) $
    • The duty cycle D is clamped to a maximum of 95% to guarantee minimum off-time for low-side conduction.
      • The register value is updated: ×OCR1A = 319, immediately adjusting the PWM pulse width sent to IN of U1.

Step 4: Multi-Tier Current Protection & Fault Handling

  • Tier 1: Software Soft-Limit (Constant Current / Foldback) If IOUT exceeds the soft current threshold set by ICTRL, the software reduces an internal headroom parameter limitCap at a rate of 50 V/s. This smoothly pulls down the effective target voltage Vtarget, shifting the converter from Constant Voltage (CV) mode to Constant Current (CC) foldback mode.
  • Tier 2: Instant Hardware Over-Current Trip (< 1 µs) If a hard short-circuit occurs, the voltage from U2 exceeds the reference set by ICTRL.
    1. Comparator U3: A output drives pin D2 (INT0) HIGH.
    2. The hardware ISR (tripISR) fires instantly, clearing port bit PB0 directly in hardware register memory (PORTB &= ~_BV(PB0)).
    3. Pin 8 (SD) drops LOW, disabling U1 and turning off both MOSFETs within microseconds.
    4. The system enters a 1-second retry cooldown (RETRY_MS). If 5 consecutive trips occur without a clean 10-second run, the system latches an OCP-LATCH fault and locks the converter OFF until manually reset by typing r in the serial terminal.
  • Tier 3: Secondary Fault Monitoring
    • OVP (Over-Voltage Protection): If VOUT > 25 V for >300 ms, an OVP fault is latched.
    • FB-LOST (Feedback Loss): If duty cycle >10%, VOUT , and IOUT for >300 ms (indicating a broken feedback voltage divider), the system latches an FB-LOST fault and shuts off PWM.

Test & Measurements

1. Signal Waveforms
The following shows the IR2104 MOSFET driver VB,HO,VS and LS signal waveforms:

IR2104 MOSFET driver VB,HO,VS and LS signal waveforms

2. Simulation and Animation Video

The following video illustrates the working of the Arduino synchronous buck converter via animation. One can see the control signals from Arduino to IR2104, the current flowing in and output of the MOSFETs. It also shows the various features and capabilities of the Synchronous DC to DC step down converter such as input and output voltage and current limits and protection, overcurrent, under-voltage detection, wait and restart, controlling the output voltage and current via potentiometer and via serial input etc.



1 min read

Post a Comment

Previous Post Next Post