The FS8205A is a dual N-channel enhancement-mode MOSFET integrated circuit, commonly utilized in battery protection circuits, power management systems, and load switching applications due to its low on-resistance and high-speed switching capabilities. It is specifically designed to act as a compact, efficient switch for protecting lithium-ion battery packs against overcharge, over-discharge, and over-current conditions.
The model uses only standard SPICE3 elements (M, R, C, D, .MODEL with LEVEL=1) and plain .SUBCKT/.ENDS, so it should work in ngspice, LTspice, KiCad (which uses ngspice) and Proteus. The parts that differ are the symbol and pin-order setup, not the model itself.
Download F8205A Proteus Library with Spice Model
Regarding the F8205A SPICE model, it is a critical component for virtual prototyping in circuit simulator software like Proteus, KiCAD, Altium designer, LTspice, Ngspice etc, allowing engineers to simulate the electrical behavior of the MOSFET within a circuit before physical implementation. Here this F8205A spice model was integrated into Proteus for test simulation. The test simulation can verify thermal performance, switching losses, and transient responses, ensuring the design meets reliability standards under various load conditions.
FS820A Bidirectional Switch Behavior Test Circuit
- Battery Protection: In lithium-ion battery management systems (BMS), a bidirectional switch is essential to independently disconnect the battery from the charger (to prevent overcharging) and from the load (to prevent over-discharging). A single MOSFET would fail to stop current flow in one of these directions due to its body diode.
- True Isolation: It provides a reliable "off" state that is immune to voltage fluctuations on either side of the switch. This is critical for safety-critical applications where you must ensure that no current can leak into or out of a power source.
- Verification in Simulation: Verifying this in Proteus is vital because it allows you to test the "blocking" capability under various fault conditions. You can simulate a scenario where the battery voltage is higher than the charger voltage (or vice versa) and confirm that the dual MOSFET configuration successfully prevents current flow. Without this verification, you risk designing a protection circuit that remains "leaky" or fails to engage during a critical over-voltage or under-voltage event.
Schematic. V3 feeds the 10 Ω resistors (still labeled RL) into S2 (pins 6/7). S1 (pins 2/3) is grounded, D is open, V1 drives G1 (pin 4) through R1, and V2 drives G2 (pin 5) through R2. That is the setup I described.
Plot. The gate timing is: G1 is on 5–10 ms and 15–20 ms, and G2 is on 10–20 ms.
The current follows:
| Window | Gates | What the plot shows | Expected |
|---|---|---|---|
| 0–5 ms | both off | almost no current | blocked |
| 5–10 ms | G1 only | positive halves only, about +40 mA | positive half passes through the body diode (DB2) |
| 10–15 ms | G2 only | negative halves only, about −40 mA | negative half passes through DB1 |
| 15–20 ms | both on | full sine, about ±100 mA | 1 V / 10.05 Ω ≈ 100 mA |
The 5–10 ms and 10–15 ms windows are mirror images, so the two FETs are matched.
About the 40 mA. My earlier estimate of 28 mA was too low. I used the datasheet's 0.72 V diode drop, but that is specified at a higher current. At 40 mA the diode drops only about 0.55 V, which gives (1 − 0.55) / 10 ≈ 45 mA, matching the plot.
The small negative blips at the negative peaks. You see them in 0–5 ms and 5–10 ms, not in the other windows or on the positive peaks. They are not a model error. When S2 swings below −0.8 V, the "off" gate (G2, tied to ground through 100 Ω) has VGS = +0.8 V or more relative to its source, so M2 turns on weakly. A real FET with Vth = 0.8 V does the same. To remove them, use a smaller sine amplitude (about ±0.5 V). The diode-clipped windows then show almost no current, which also demonstrates blocking cleanly. For a figure for your blog, I'd keep ±1 V and note the effect in the caption.
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