This is a note on how boost converter IC like MT3608 internal circuit works. For example, the MT3608 IC has 6 pins IN, SW, EN, FB, VSS and NC. Other voltage converter IC have similar pins. The VSS is the ground pin, and NC is No Connection pin which means no connection is required. EN is enable which needs to be held high to enable the chip and IN pin is the input dc supply pin which we want to step up. So, the main pins actually are the SW and FB. The FB is the feedback input pin, which samples the output signal and feed backs into the circuit. The SW pin is the switching pin which connects to the junction of diode and inductor of a boost converter.
Now, below the circuit diagram shows the internal circuit schematics of boost converter/step up converter IC like MC3608.
The error signal $V_{err}$ is then compared with sawtooth signal $V_{sum}$ and PWM signal with duty cycle proportional the $V_{err}$ magnitude is created.
Now, below the circuit diagram shows the internal circuit schematics of boost converter/step up converter IC like MC3608.
Note that the above circuit also shows the external circuit component besides the internal IC circuit. Compare the first and this 2nd circuit to find out which are external components.
So here I am going to tell the overall operation of this step up or boost converter. The input voltage 3.7V which is to be stepped up is connected across the VIN+ and VIN- pins. The capacitor C1 acts as noise filter which is connected across the battery. The EN and the IN pins of the internal boost converter IC is connected to the 3.7V dc power source. The 22uH inductor is also connected to the +ve side of the voltage input pin. After the inductor is the diode which is facing towards the output voltage node. Between the diode and inductor is connection to the switch SW pin of the internal boost converter IC. At the output we have a noise decoupling capacitor C2 of 22uF. RL is the load and the boosted voltage appears across the VOUT+/VOUT-.
- Power On Sequence with Initial Condition
At t = 0 everything is at zero: $V_{out}$ = 0, $I_L$ = 0, all capacitors $C_{comp}$, $C_d$ and $C_{d1}$ are discharged, $V_{err}$ = 0, and $Q$ = 0.
- VIN below 1 V. Both EN (Enable) and UVLO (Under Voltage Lock Out) comparators outputs are low since $V_{in}$ is below 1V, lower than both comparator reference voltages are 1V and 1.9V, so it does not exceed both comparator reference voltages. So, the output of AND gate $V_{on}$= 0V (Logic 0), The NAND output $V_{on}$ is 5V (Logic 1), so $V_{rst}$ = 5V (Logic 1) and $Q$ is held at 0. The switch cannot turn on whatever the clock does.
- The converter is still not isolated. Even with Q1 off, there exist direction path from input to output, that is, $V_{in}\rightarrow L \rightarrow D \rightarrow V_{out}$ is a direct path from the battery. It is an LC circuit with $Z_0 = \sqrt{\frac{L}{C}} = \sqrt{\frac{22\,\mu\text{H}}{22\,\mu\text{F}}} = 1\,\Omega$ and $f_0 = \frac{1}{2\pi\sqrt{LC}} = 7.2\,\text{kHz}$. The inrush peaks near $\frac{V_{\text{in}} - V_f}{Z_0}$, which is a few amps in the ideal limit (less after the battery resistance and ESR). COUT can overshoot to about $2(V_{in}-V_{fb})$, roughly 6.5 V, before the diode blocks. This is normal for a boost converter and is not caused by the controller.
- VIN above 1.9 V. In this case, $V_{on}$= 5V (Logic 1), so RESET releases as long as $V_{or} $= 5V (Logic 1) and $V_{dc}$ = 5V (Logic 1).
- Vref starts from V1, a pulse source. If its rise time is non-zero, that is soft start. At first $V_{fb} ≈ 0$, so $V_e = V_{ref}-V_{fb} > 0$(note:$V_{err} = 100\times V_e$)$, C_{comp}$ charges and $V_{err}$ rises.
- While Verr is still low, $V_{sum}$ is already above $V_{err}$, so $V_{pwm}$ = 0. The only thing keeping Q1 on is the 60 ns delay on $\bar{Q}$. The first pulses are therefore a few tens of ns wide, which is the minimum on time.
- Verr climbs, the pulse width grows, $I_L$ builds, and $C_{OUT}$ is pumped up toward 15 V. As $V_{fb}$ approaches $V_{ref}$, $Ve \rightarrow 0$ and the loop settles.
- Error Amplifier with Compensation Network
Once the circuit is powered up, the error amplifier compares the sampled feedback output $V_{fb}$ with $V_{ref}$=0.6V signal. The output signal $V_{err}$ is given by,
$$V_{err}= A_v(V_{ref}-V_{fb})$$
where $A_v$ is voltage gain, set to 100 in this circuit, $V_{ref}$=0.6V is voltage reference and $V_{fb}$ is the output feedback signal which is defined as,
$$V_{fb}= V_{in} \frac{R_2}{R_1+R_2}$$
- If $V_{ref} > V_{fb}$ then $V_{err}$ is +ve, this allows to create PWM signal that turns on/off the N-channel MOSFET switch with some duty cycle.
- If $V_{ref} \leq V_{fb}$ then $V_{err}$ is -ve, this leads to PWM signal with duty cycle 0, that is no PWM signal, and the MOSFET switch is off.
The following graph shows the $V_{err}$,$V_{ref}$,$V_{fb}$ signals waveform for $ V_{out}$=12V and $ V_{in}$=3.7V.
The error signal $V_{err}$ is then compared with sawtooth signal $V_{sum}$ and PWM signal with duty cycle proportional the $V_{err}$ magnitude is created.
Loop Compensation Network
- PWM Comparator
The PWM signal $V_{pwm}$ generated by the PWM comparator by comparing magnitude of $V_{err}$ and $V_{sum}$ signals, where $V_{sum}$ is the signal generated by adding $V_{saw}$ signal and $V_{cs}$ signal.
$$V_{sum}= V_{cs} + V_{saw}$$
$$V_{pwm}= [ V_{err} > V_{sum}]$$
- OR Gate
It forces Vor high for about 42 ns after turn-on. This is leading-edge blanking and a minimum on-time, so the turn-on spike or a very low Verr cannot end the pulse instantly.
|
Delayed Vqbar |
Vpwm |
Vor (Output) |
|
0 |
0 |
0 |
|
0 |
1 |
1 |
|
1 |
0 |
1 |
|
1 |
1 |
1 |
- NAND Gate
It has three inputs $V_{on}$, $V_{or}$ and $V_{dc}$ and one output $V_{rst}$. The $V_{dc}$ forces a reset at the end of the maximum-duty window, which limits D.
Since it is a 3-input NAND gate, the output is low (0) only when all three inputs are high. Otherwise, it is high.
|
Vdc |
Vor |
Von |
Vrst (Output) |
|
0 |
0 |
0 |
1 |
|
0 |
0 |
1 |
1 |
|
0 |
1 |
0 |
1 |
|
0 |
1 |
1 |
1 |
|
1 |
0 |
0 |
1 |
|
1 |
0 |
1 |
1 |
|
1 |
1 |
0 |
1 |
|
1 |
1 |
1 |
0 |
- D Flip Flop
The function of the D flip flop is to turn on/off the MOSFET switch at the frequency set by the incoming clock which for MT3608 is 1.2MHz.
In this switching power supply controller, the DFF acts as the primary PWM latch:
- CLK Input: Driven by the clock oscillator(CLK), the rising edge of the clock initiates a new switching cycle by setting the Q output HIGH, which turns on the power MOSFET gate drive.
- DATA Input: Tied to a fixed high/low state or power rail to determine the state to be clocked through.
- RESET Input: Driven by the NAND gate output (VRST). When the current limit, maximum duty cycle, or PWM comparator trips, VRST goes high, immediately resetting Q LOW to terminate the power pulse before the next clock cycle.
- $Q$ and $ \bar{Q}$: Outputs: Q drives the gate driver path, while $ \bar{Q}$ feedback to logic/blanking circuits via the RC network($R_d$, $C_d$)
Truth Table for a Standard D-Type Flip-Flop (with Asynchronous Reset)
|
RESET |
CLK |
D |
$Q$ (Next State) |
$ \bar{Q}$ (Next State) |
Description |
|
1 |
X |
X |
0 |
1 |
Asynchronous Reset (Forces Q low immediately, active state in your circuit) |
|
0 |
$\uparrow$ (Rising) |
0 |
0 |
1 |
Latches a Logic 0 |
|
0 |
$\uparrow$ (Rising) |
1 |
1 |
0 |
Latches a Logic 1 |
|
0 |
0 or 1 |
X |
Q (prev) |
$ \bar{Q}$ (prev) |
Hold State (No change between clock edges) |
- MOSFET Switch
It regulates the input voltage $V_{in}$ to the output determined by duty cycle determined by the PWM comparator. The 10Ω resistor is gate resistor $R_g$ to limit current into the gate and $R_{pd}$ 100kΩ is pull-down to keeps the N-channel MOSFET switch Q1 off if the gate drive state is undefined.
- Current Sense Amplifier
The current sense amplifier senses the voltage across the current-sense resistor $R_s$ ($V_{sense} = I_L R_s$) with a gain $A_{cs}$(=40).
The output of the current sense op-amp passes through a low-pass RC filtering/delay network formed by $R_{d1}$ and $C_{d1}$. The resulting waveform $V_{cs}$ as a function of the amplifier output $V_{ampout}$ and amplifier output voltage equation are below
Capacitor Voltage Equation:
$$V_{cs}(t) = V_{ampout}(0) + (V_{ampout}(\infty) - V_{ampout}(0)) (1 - e^{-\frac{t}{R_{d1}C_{d1}})$$
Amplifier Output Voltage Equation:
$$V_{\text{amp\_out}} = A_{\text{cs}} \cdot (I_L \cdot R_S) = 40 \cdot I_L \cdot R_S$
Summed Signal Equation:
This summed signal is compared with the PWM comparator output:
$$V_{sum}=V_{cs}+V_{saw}$$
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