Simulation and Design of MP1584 IC Buck Converter IC

This is a note on how the MP1584 Buck Converter IC works with design and test simulation and circuit animation.

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The following shows the MP1584 IC internal circuit diagram.

Function of Components

1. Parent circuit (external components)

Ref	Value	Connected between	Function / role
B1	12 V	VIN – GND	Input supply
C1	10 µF	VIN – GND	Input decoupling
C4	100 nF	SW – BST	Bootstrap capacitor; holds about 5 V above SW for the gate drive
D1	SS34	GND (anode) – SW (cathode)	Catch diode; carries inductor current while Q1 is off
R8	25 mΩ	SW – L1_IN	Series resistance (probably inductor DCR)
L1	22 µH	L1_IN – VOUT	Energy storage; with C2 forms the LC output filter
C2	22 µF	VOUT – GND	Output filter capacitor
R1	412 kΩ	VOUT – FB	Upper feedback divider resistor
R2	40.2 kΩ	FB – GND	Lower feedback divider resistor; sets VOUT ≈ 9.0 V
R3	125 kΩ	COMP_RC – GND	Compensation resistor
C3	150 pF	COMP – COMP_RC	Compensation capacitor (series with R3 from COMP to GND)
R5	100 kΩ	VIN – EN	Enable divider, top
R6	24.9 kΩ	EN – GND	Enable divider, bottom; EN ≈ 2.39 V at 12 V in
R7	25 Ω	VOUT – GND	Load, about 0.36 A
R4	100 kΩ	GND – GND	No effect (both ends grounded); likely an unused FREQ resistor placeholder

2. Subcircuit U1: power stage and bootstrap

Ref	Function / role	Inputs	Output
U1_Q1 (NMOS)	High-side power switch	Drain from Q1_DRAIN, gate from Q1_GATE	Source drives SW
U1_R_SENSE (25 mΩ)	Senses switch current	VIN	Q1_DRAIN
U1_RG (50 Ω)	Gate resistor, slows the edge	GATE_DRIVE	Q1_GATE
U1_RPD (100 kΩ)	Gate pull-down; keeps Q1 off when undriven	Q1_GATE	SW
U1_C1 (100 pF)	SW parasitic capacitance	SW	GND
U1_SUM2	Level shift so the gate floats with SW	DRIVE_LOGIC + SW	GATE_DRIVE
U1_V5 (5 V)	Floating 5 V reference on SW	SW	SW_PLUS_5V
U1_U7 (BST CMP)	Detects when BST has dropped below SW + 5 V	− SW_PLUS_5V, + BST	Q2_GATE
U1_Q2 (PMOS)	Recharges C4 from VIN when needed	Source from VIN, gate from Q2_GATE	Q2_DRAIN
U1_D1 (diode)	Stops BST discharging back through Q2	Q2_DRAIN	BST

3. Subcircuit U1: control loop

Ref	Function / role	Inputs	Output
U1_V1	Soft-start reference, 0 → 0.8 V in 1.5 ms	none (source)	SS_REF
U1_U1 (ERR_AMP)	Transconductance error amp (≈ 60 µS)	− FB, + SS_REF	COMP
U1_U6 (ISENSE_AMP, ×4.44)	Amplifies the voltage across R_SENSE	− Q1_DRAIN, + VIN	ISENSE_OUT
U1_R_BLANK + U1_C_BLANK	Leading-edge blanking filter (1 kΩ + 100 pF)	ISENSE_OUT	Vcs
U1_V2	Slope-compensation sawtooth, 0–80 mV	none (source)	RAMP (stacked on OFFSET_0V9)
U1_V3 (0.9 V)	Offset that sets the COMP operating range	none (source)	OFFSET_0V9
U1_SUM1	Adds current signal and ramp	Vcs + RAMP	Vsum
U1_U2 (PEAK_CURRENT_CMP)	Goes low when Vsum reaches COMP (peak current reached)	− Vsum, + COMP	PEAK_CMP_OUT
U1_V4	900 kHz clock, 20 ns low pulses	none (source)	CLK
U1_U3 / U1_U4 (SR latch)	The clock sets it (switch on); PEAK_CMP_OUT resets it (switch off)	PEAK_CMP_OUT, CLK	LATCH_Q / LATCH_QB
U1_U5 (inverter)	Turns the latch output into a switch-on request	LATCH_Q	ON_CMD

4. Subcircuit U1: enable, UVLO and gating

Ref	Function / role	Inputs	Output
U1_V6 (3 V)	UVLO threshold reference	none	UVLO_REF
U1_U9 (UVLO_CMP)	Lockout: high when VIN > 3 V	− UVLO_REF, + VIN	UVLO_OK
U1_V7 (1.35 V)	Enable threshold reference	none	EN_REF
U1_U8 (EN_CMP)	High when EN > 1.35 V	− EN_REF, + EN	EN_OK
U1_V8 (3 V) + U1_R1 (“3M”)	Internal pull-up on EN	EN_PULLUP_3V	EN
U1_U10 (AND)	Both enable and UVLO must be good	UVLO_OK, EN_OK	ENABLE_OK
U1_U11 (AND)	Lets the switch-on request through only when enabled	ENABLE_OK, ON_CMD	DRIVE_LOGIC

Switching cycle in names:

CLK sets the latch, so ON_CMD goes high. If ENABLE_OK is also high, DRIVE_LOGIC goes high.
SUM2 turns that into GATE_DRIVE (DRIVE_LOGIC + SW), which drives Q1_GATE through RG.
Current rises through R_SENSE and shows up as Vcs, which is added to RAMP to give Vsum.
When Vsum reaches COMP, PEAK_CMP_OUT goes low and resets the latch, so Q1 turns off.
The error amp (FB versus SS_REF) sets COMP, which closes the regulation loop.

Switching Frequency, Inductor Selection and Output Voltage Feedback Resistors Values

Here is a brief summary with the equations.

1. Switching frequency

The MP1584 frequency is set by a resistor from FREQ to GND. With RFREQ = 100 kΩ the oscillator runs at 900 kHz, and the programmable range is 100 kHz to 1500 kHz. The datasheet gives this as a curve (RFREQ vs. fSW), not a formula, so read other values off that graph. rs-online we-online

With fSW = 900 kHz and Vin = 12 V, Vout = 9 V:

Duty cycle: D = Vout / Vin = 9 / 12 = 0.75
Period: T = 1 / fSW ≈ 1.11 µs
t_on = D × T ≈ 833 ns, t_off ≈ 278 ns

In your model the frequency comes from F=900k (V4/V2), not from R4, so changing R4 won’t change the simulation.

2. Inductor selection

Choose the ripple current as 30–40% of the maximum load current:

ΔIL = (0.3 to 0.4) × I_load(max)
L = (Vout / (fSW × ΔIL)) × (1 − Vout / Vin)
Peak current: I_peak = I_load + ΔIL/2. The inductor’s saturation current must be above this, and above the IC’s current limit if you plan to load it to 3 A.

For your test load, I_load = 9 V / 25 Ω = 0.36 A, so ΔIL ≈ 0.11–0.14 A:

L = 9 / (900k × 0.12) × 0.25 ≈ 20.8 µH, so 22 µH is the nearest standard value.

With L = 22 µH, the actual ripple is ΔIL = Vout(1 − D) / (fSW × L) = 2.25 / (900k × 22 µ) ≈ 0.114 A, which is about 32% of 0.36 A. The peak is about 0.42 A. At the full 3 A rating, 22 µH gives only about 4% ripple. That is fine for regulation but lower than the usual guideline.